In a planar transistor, source and drain regions may be formed on the left and right sides of a central gate. In this transistor structure, when current flows from the source to the drain, leakage current is generated, which flows to the semiconductor substrate. The leakage current causes an increase in power consumption. Also, a hot carrier phenomenon at the edge of the gate severely affects the reliability of the device.
Accordingly, development of a method of forming a transistor which reduces leakage current and hot carrier effects is required. Also, development of a method of forming a transistor device which improves current performance in the same area is required.